Dr. Michael Manzke's 3BA5 - Computer Engineering

[Trinity College] [Department of Computer Science] [GV2] [Michael Manzke]

3BA5 Computer Engineering
Semester 1 - Microprocessor Systems Engineering

HOME

3BA5

CS7ET02

Lecturer: Dr. Michael Manzke

`Duration: 1 semester, 3 hours per week.`
`Time Table: Junior Sophister 2005-2006`
`Software: VHDL (XILINX - ISE Logic Design Tools), Mentor Graphics, ModelSim`
`Prerequisites: 1ba3, 1ba4, 2ba4, VHDL`
Aims of Course: To learn the architecture, organization and design of high performance processing systems with emphasis on pipelined systems.
Course Work: Two projects using VHDL ModelSim.
Contents: Bit-parallel memory and arithmetic, I/O processors, interleaved memory, cache memory, instruction look-ahead, multiple functional units, instruction pipelines, pipeline functional units, processor arrays, multiprogramming, timesharing, multiprocessing, data-flow, Flynn's taxonomy.
Textbooks:
[1]	[2]	[3]	[4]	[5]
[1]"Computer Architecture - Single and Parallel System", Mehdi R. Zargham, S-LEN 500.164 N68 [2] "Logic and Computer Design Fundamentals",M. Mano & C. R. Kime, S-LEN 621.392 N71 [3] "Computer Architecture - A Quantitative Approach", John L. Hennessy & David A.Patterson, S-LEN 500.164 N0995 [4] "Computer Organisation and Design", John L. Hennessy & David A.Patterson, 500.164 N85 [5] "Introductory VHDL From Simulation to Synthesis", Sudhakar Yalamanchili, S-LEN 621.392 P1 This computer engineering course follows mostly the material presented in textbook [1]. Textbooks [2,3,4] complement the syllabus. Textbook [5] or equivalent could help with the VHDL programming.
`Lecture Notes:`
Don’t try this @ home! The lecture notes are rather large. Before you struggle to upload the files at home please upload them onto a zip-disk in College and print them afterwards. It takes only seconds.
3ba5 students are expected to read the following material (Exam relevant): Students should revise material covered in 2BA4 by reading Chapter 5 “The Processor: Datapath and Control” in " Computer Organisation and Design", John L. Hennessy & David A. Patterson, 500.164 N85. Appendix C “Mapping Control to Hardware” in the same textbook provides information that complements ideals presented in the 3ba5 lecture. "Computer Architecture - A Quantitative Approach", John L. Hennessy & David A.Patterson, S-LEN 500.164 N0995, Appendix C – A Survey of RICS Architectures for Desktop, Server, and Embedded Computers. "Computer Architecture - A Quantitative Approach", John L. Hennessy & David A.Patterson, S-LEN 500.164 N0995, Appendix D – An Alternative to RISC: The Intel 80x86.
Michaelmas Term (Week 1-9): 1^stLecture, Tuesday 11^th October 2005 2^ndLecture, Wednesday 12^th October 2005 3^rdLecture, Wednesday 12^th October 2005 4^thLecture, Tuesday 18^th October 2005 5^thLecture, Wednesday 19^th October 2005 VHDL Tutorial (Control Unit), Wednesday 19th October 2005 6^thLecture, Tuesday 25^th October 2005 7^thLecture, Wednesday 26^th October 2005 VHDL Tutorial (Control Unit), Wednesday 26th October 2005 8^thLecture, Tuesday 1^st November 2005 9^thLecture, Wednesday 2^nd November 2005 Tutorial One, Wednesday 2nd November 2005 Tuesday 8^th November 2005 - Lecture Postponed Wednesday 9^th November 2005 - Lecture Postponed 10^thLecture, Tuesday 15^th November 2005 11^thLecture, Wednesday 16^th November 2005 12^thLecture, Wednesday 16^th November 2005 VHDL Tutorial (CSA/CLA), Wednesday 16th November 2005 13^thLecture, Tuesday 22^th November 2005 14^thLecture, Wednesday 23^rd November 2005 Tutorial (Project 1a), Wednesday 23rd November 2005
Project 1a - Due: Friday, 9^th December 2005, before 3:30pm Please submit a paper copy of your VHDL code and an electronic copy of the VHDL code, test-benches and simulation results to the office in the Computer Science Department before 3:30pm on Friday, 9^th December 2005.
We started this project in the Tutorial on the 23^rd November 2005. At that point I provided you with the following VHDL/Schematic 3ba5_schematic_1a.pdf file that shows one possible implementation. You may design your our solution as long as it generates the waveforms shown in the 3ba5_wave_1a.pdf file.
15^thLecture, Tuesday 29^th November 2005 16^thLecture, Wednesday 30^th November 2005 Tutorial One, Wednesday 30th November 2005 Only available as paper copy (distributed in class)!
Project 1b VHDL Floating-point Pipeline Design Please find a copy of the Project 1b description here. A paper copy was distributed in class on Tuesday, 6^th December 2005. DUE: Monday, 16^th Janury 2006. Please submit a paper copy of your VHDL-code and test-bench-waves and an electronic copy of your project including all simulation results to the office in the Computer Science Department before 4:00 pm. Late submissions will receive no credit. You are required to demonstrate your VHDL simulation in operation during lab. Hours, on Wednesday, 18^st January 2006.
17^thLecture, Tuesday 6^th December 2005 18^thLecture, Wednesday 7^th December 2005 Tutorial (Project 1b), Wednesday 7^th December 2005
Hilary Term (Week 1-3): 19^thLecture, Tuesday 10^th January 2006 20^thLecture, Wednesday 11^th January 2006 Tutorial Two, Wednesday 11th January 2006 21^stLecture, Tuesday 17^th January 2006 22^ndLecture, Wednesday 18^th January 2006 Project 1b Demo, Wednesday 18^th January 2006 23^rdLecture, Tuesday 24^th January 2006 24^thLecture, Wednesday 24^th January 2006 25^thLecture, Wednesday 24^th January 2006
Project 2 NEW Computer Engineering Essay The essay should relate material covered in Part I of 3BA5 Computer Engineering to: Section 3.10 "Putting It All Together: The P6 Microarchitecture” in “Computer Architecture : Quantitative Approach / John L. Hennessy, David A. Patterson ; with contributions by David Goldberg, Krste Asanovic. Counter Reserve (Hamilton) 500.164 N09952;1” and the following paper: Decisive Aspects in the Evolution of Microprocessors by Dezsö Sima Your discussion should include all the topics that were presented in the first semester of the 3BA5 course which matches material examined in the book section or the paper such as pipelining, superscalar, superpipeline, scheduling … The essay must have between 2000 and 2500 words. DUE: Wednsday, 22^nd February 2006. Please submit a paper copy of your* essay to the office in the Computer Science Department before 4:00 pm. Late submissions will receive no credit.
T H E E N D
There is a link to the departmental course entry here.