Supervisor: Michael Manzke

All my students are encouraged to use the Concurrent Version System (CVS) and LaTeX for their project and write-up.  

 Application of Tomasulo’s Method for FPGA Computations

 Shonagh Hurley

The aim of this project is to display the phenomenal impact Tomasulo’s Method has had on modern day computer architecture. To do this, a datapath implemented with hardware, proposed by the Tomasulo Method, was built in the hardware description language, VHDL. There are two phases to this dissertation: Firstly, the various stages of research are outlined, focusing on advanced pipelining features. Secondly, a detailed design description is given, outlining the specifications, requirements, design procedure and testing stages. Overall, the project was very challenging and to date I have a fully simulated and synthesised version of my design. The top-level code, however, is fully functioning for only one instruction. All internal entities have been tested and a small amount of adjustment would allow application to other instructions.

Shonagh's Report

 

Synthesisable VHDL Model for SCI Cache-coherence Protocols

Oliver Pugh

The Scalable Coherent Interface (SCI) is an ANSI/IEEE standard that defines a high performance interconnect technology, providing solutions for a wide range of applications. Among other features, the standard provides optional cache coherence, using a distributed-directory approach. The highly sophisticated cache coherence protocols, designed to be implemented in hardware, are renowned for their scalability. This report outlines a project which simulates the cache coherence protocols in a small network, using VHDL.

Oliver's Report

 

Design, Implement and Evaluate the Performance of a FPGA based Kalman Filter

  Mary Martha Howlett

The overall aim of this project was to design, implement and evaluate the performance of a kalman filter using FPGAs. The projects main concern is the design of a synthesisable VHDL model for the algorithm which defines this filter. From the project viewpoint it was not essential for me to become an expert in minimum mean square error filtering and state space methods. What was required, however, was for me to be familiar with the algorithm, that defines the kalman filter. The set of equations, their relevance to one another and indeed the overall functionality of the algorithm required complete comprehension. If successful the resulting program would then be implemented with field programmable gate arrays, enablingthe end result to be appreciated visually.

Mary's Report

Analogue Dynamics Engine (ADE)

Muiris Woulfe

This report outlines the design and implementation of the Analogue Dynamics Engine (ADE). The ADE is a physics engine constructed from a hybrid, analogue and digital, computer. Software physics engines are becoming increasingly common in computer games, and the ADE was designed as a hardware equivalent to these software engines. Analogue computers, although currently rare, have useful properties such as their ability to evaluate functions in realtime. The physics engine exploits this functionality while using digital components to provide reconfigurability. The core hybrid computer was constructed by connecting twenty nine custom designed reconfigurable analogue cells to thirty two bus lines, using programmable interconnect. Each cell can performinversion, integration, addition and multiplication. At the periphery of this computer lie two ADCs and two DACs, so that the hybrid computer may provide a digital interface. In order to make the engine suitable for use with games, it was decided to make simulations multiplexable, so that multiple simulations could be run "concurrently". This requires simulations to be executed faster than real-time. Additionally, state must be saved and restored, which was achieved through replicating the capacitors. Finally, this report analyses the viability of this project for use in computer games. Ultimately, it was determined that an analogue computer could become a viable replacement for the software physics engines in use today. In fact, it offers benefits that cannot be obtained using today’s software physics engines.

Muiris's Report

 

Synthesisable VHDL Model of 3D Graphics Transformations

Daniel McKeon

Since their emergence only 15 years ago, Field Programmable Gate Arrays, have gone from strength to strength in the domain of reprogrammable hardware. As they improve, they grow in speed, size and ability. All these factors mean FPGAs are becoming more useful in areas where fixed hardware was the basis before. One such area is in 3D Graphic rendering, where research is underway as to how programmability and specifically reprogrammable FPGAs can help to improve the performance of graphic processing units. One area FPGAs can assist is through the handling of complex algorithms on inexpensive, dynamically reconfigurable hardware. In my project I attempt to put this idea into practice by implementing a design for the transformations and projections of 3D vectors onto a Spartan 3 FPGA. I attempt to do this through a hardware description language (VHDL) and explore the problems, solutions and alternatives faced when approaching such a project.

Daniel's Report

 

 Advanced Teaching Instruction Set Processor

Diarmaid O'Cearuil

The goal of this project was to design a micro-programmed microprocessor with its own instruction set as a teaching tool
for 2nd year computer science students. Following on from Laura Redmond's project last year, I started by changing the existing functional components and then adding new ones. I changed and made additions to the control circuitry in order to micro-program the new functional components. 

The next part of the project was to download the design onto an FPGA. The final part of the project was to design a GUI that would be a tutorial for the students and allow the lecturer/student to create a new microprocessor project with the option of not including certain components so that the students would have to design these themselves. The report outlines the difficulties of simulating a micro-programmed
microprocessor and transfering the design to the board.

Diarmaid's Report

 

 Synthesisable VHDL model of a Java Virtual Machine for HAL

Louise Annamarie Reilly

The aim of this final year project was to implement a Java Virtual Machine on an FPGA. The FPGA is located on a hardware learning board used by second year Computer
Science and third year Engineering students as part of their
coursework. The introduction of a JVM to this hardware will enable students to program the FPGA with Java in place of lower level languages such as Assembly or VHDL, VHDL being the language currently in use. This project is part of a continuing effort to upgrade the learning boards from the Motorola MC68008 microprocessor technology which has been part of the course for many years. It built upon the final year project of Ross Brennan. His project involved implementing a RISC microprocessor in place of the CISC architecture which was there and resulted in a prototype project board being designed and assembled. It was one of these boards which was used here. The JVM implemented on the upgraded board originated as part of a PhD thesis at the Technical University of Vienna, Austria. It is an optimized JVM designed specifically for Altera software and the Cyclone board. As part of the project the original VHDL code was altered to run on Xilinx software and the Virtex-II board which the students will be working with.

Louise's Report

There is a link to the departmental final year project page here.