// Weste & Eshraghian CMOS Process
//
// Design Rules for lambda=0.5microns
//
TITLE "Weste&Eshraghian CMOS (lambda=0.5micron) design rules"
//
// Layer Definitions
//
substrate = ALL NOT Nwell
ndiff = Nplus AND substrate
vddn = Nwell AND Nplus
vssp = Pplus AND substrate
pdiff = Nwell AND Pplus
diff = Nplus OR Pplus
active = ndiff OR pdiff
ngate = Poly AND ndiff
pgate = Poly AND pdiff
gate = ngate OR pgate
wired = Nplus OR Pplus
wire = wired OR Poly
vmetal = Metal2 OR Metal3
//
// All lines must be vertical, horizontal or at forty-five degrees
//
Skew_Edges{ DRAWN SKEW }
//
badptran = Poly AND vssp
badntran = Poly AND vddn
//
// Bad layer combinations
//
Bad_Gates { badntran OR badptran }
//
// Minimum Widths
//
// A.1
A1_Nwell_Width { INTERNAL Nwell < 5 }
// B.1
B1_Active_Width {
  INTERNAL Nplus < 1.5
  INTERNAL Pplus < 1.5
}
// C.1
C1_Poly_Width { INTERNAL Poly < 1 }
// E.1
E1_Cut_Width { INTERNAL Ccut < 1 }
// F.1
F1_Metal1_Width { INTERNAL Metal1 < 1.5 }
//
// Minimum Separations
//
// A.2
// N-Wells at same potential
A2_Nwell_Sep { EXTERNAL Nwell < 3 }
// A.3
// N-Wells at different potentials
A3_Nwell_PD  { EXTERNAL Nwell < 4 }
// B.2 (n+)
B2_Active_Sep {
  EXTERNAL Nplus < 1.5
  EXTERNAL Pplus < 1.5
}
// C.2
C2_Poly_Sep { EXTERNAL Poly < 1 }
// D.4
D4_Gate_Sep { EXTERNAL gate < 1.5 }
// E.2, E.3
E2_Cut_Sep { EXTERNAL Ccut < 1 }
// F.2
F2_Metal1_Sep { EXTERNAL Metal1 < 1.5 }
//
// B.5
B5_Nwell_ndiff_Sep {
 EXTERNAL Nwell ndiff < 2.5
 COINCIDENT EDGE Nwell ndiff
 }
// B.6
B6_Nwell_vssp_Sep {
  EXTERNAL Nwell vssp < 1.5
  COINCIDENT EDGE Nwell vssp
 }
// C.3
C3_Poly_Active_Sep {
  EXTERNAL Poly Nplus < 0.5
  EXTERNAL Poly Pplus < 0.5
  COINCIDENT EDGE Poly Nplus
  COINCIDENT EDGE Poly Pplus
}
// E.7
E7_gate_Cut_sep {
   EXTERNAL gate Ccut < 1
   COINCIDENT EDGE gate Ccut
 }
//
// Transistor Extensions
//
// C.4
C4_Gate_Ext {
  ENCLOSURE active Poly < 1
}
//
// Contact Overlaps
//
// B.3
B3_NW_pdiff_Overlap {
  ENCLOSURE pdiff Nwell < 2.5
  COINCIDENT EDGE pdiff Nwell
 }
// B.4
B4_NW_vddn_Overlap {
  ENCLOSURE vddn Nwell < 1.5
  COINCIDENT EDGE vddn Nwell
 }
// E.4, E.5
E4_wire_Cut_Ovl {
  ENCLOSURE Ccut wire < 1
  COINCIDENT EDGE Ccut wire
 }
// E.6
E6_Metal1_Cut_Ovl {
  ENCLOSURE Ccut Metal1 < 0.5
  COINCIDENT EDGE Ccut Metal1
 }
//
Cut_Conn {
  Ccut NOT INSIDE Metal1
  Ccut NOT INSIDE wire
}
Via_Conn {
  Via NOT INSIDE Metal1
  Via NOT INSIDE vmetal
}
//
//
// Connectivity
//
// Direct Connections
//
//CONNECT Nplus Nwell     MASK
//CONNECT Pplus substrate MASK
//
// Cut/Via connections
//
nsd = ndiff NOT Poly
CONNECT Metal1 nsd  BY Ccut MASK
//ATTACH  Nplus nsd MASK
CAPACITANCE INTRINSIC nsd [0.0001 0.0005] MASK
RESISTANCE SHEET nsd [50 0] MASK
//
psd = pdiff NOT Poly
CONNECT Metal1 psd  BY Ccut MASK
//ATTACH  Pplus psd MASK
CAPACITANCE INTRINSIC psd [0.0001 0.0005] MASK
RESISTANCE SHEET psd [25 0] MASK
//
CONNECT Poly gate MASK
ATTACH  Poly gate MASK
CONNECT Metal1 Poly   BY Ccut
CAPACITANCE INTRINSIC Metal1 [.00001 0]
CONNECT Metal2 Metal1 BY Via
CAPACITANCE INTRINSIC Metal2 [.000005 0]
CONNECT Metal3 Metal2 BY Via
CAPACITANCE INTRINSIC Metal3 [.0000025 0]
//
CAPACITANCE ORDER nsd psd Poly Metal1 Metal2 Metal3 MASK
CAPACITANCE ORDER Poly Metal1 Metal2 Metal3 DIRECT
//
// Devices
//
DEVICE mp (pmos) gate gate(G) psd(S) psd(D) [0.5]
DEVICE mn (nmos) gate gate(G) nsd(S) nsd(D) [0.5]
//
// Parasitics (from Weste & Eshraghian)
//
// Sheet Resistance (min, avg, max)
// (W&E p177)
//
// Diffusion 10, 25, 100
// Polysilicon 15, 20, 30
// Metal1/Metal2 0.05, 0.07, 0.1
// Metal3 0.03, 0.04, 0.05
//
// Capacitance (area, perimeter)
// (W&E p188)
//
// Nplus 2E-4pF/um^2, 4E-4pF/um
// Pplus 5E-4pF/um^2, 4E-4pF/um
//
// Oxide and Conductor thicknesses (Angstroms)
// (W&E p197)
//
// Thin-oxide     200
// Field-oxide   6000
// Polysilicon   3000
// M1-poly-oxide 6000
// Metal1        6000
// M1-M2-Oxide   6000
// Metal2       12000
// Passivation  20000
//
// Typical Capacitances (10-18F/um)
// (W&E p202)
//
// ndiff perimeter 400
// pdiff perimeter 400
//
// Typical Capacitances (10-18F/um^2)
// (W&E p202)
//
// ndiff area 300
// pdiff area 500
// gate 1800
// poly over field 50
// m1 over field 30
// m1 to poly 60
// m1 to diff 60
// m2 to subs 20
// m2 to m1 50
// m2 to poly 30
// m2 to diff 30
// m3 to subs 10
// m3 to m2 30
// m3 to m1 15
// m3 to poly 12
// m3 to diff 10
//